International Journal of Circuits, Systems and Signal Processing

   
E-ISSN: 1998-4464
Volume 15, 2021

Notice: As of 2014 and for the forthcoming years, the publication frequency/periodicity of NAUN Journals is adapted to the 'continuously updated' model. What this means is that instead of being separated into issues, new papers will be added on a continuous basis, allowing a more regular flow and shorter publication times. The papers will appear in reverse order, therefore the most recent one will be on top.

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Volume 15, 2021

Title of the Paper: Design and Implementation of 64-bit SRAM and CAM on Cadence and Open-source environment

Authors: N. Shylashree, Yatish D. Vahvale, N. Praveena, A. S. Mamatha

Pages: 586-594 

DOI: 10.46300/9106.2021.15.65     XML

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Abstract: Low-power IC design has become a priority in recent years because of the growing proliferation of portable battery-operated devices, bringing Static Random-Access Memory (SRAM) and Content Addressable Memory (CAM) into play. In today's SoCs, embedded SRAM units have become a necessary component. There is a lack of chips in the current world and to manufacture chips there is the requirement of Electronic Design Automation(EDA) tools that can perform better. In this paper, the main motive is to showcase the performance of open-source tools available currently which can still generate the required output with no cost. In this new era of fast mobile computing, traditional SRAM cell designs are power-demanding and underperforming. Rather than lowering manufacturing costs through high-volume production, specialty memory give cost-effective alternatives through architecture. Specialty memory devices enable the designer to address issues like board area, important timing, data flow bottlenecks, and so on in ways that high-volume regular memory devices cannot. Implementation of memory devices on Cadence environment and open-source environment to check the compatibility and compare the power, area, and delay of both 64-bit SRAM and CAM also analysing and validating the results of both the memory devices in this paper. For SRAM in a cadence environment, the calculated power, area, and slack have improved values, namely 0.145mW, 1104.3um2, and positive slack of 6636. Furthermore, the power for 64-bit CAM in a cadence context is nearly identical to those for an open-source environment ~0.8mW. In an open-source environment, the calculated slack for CAM is 4.74.