Conference Topics
Contributions related, but not limited, to the following topics of interest are welcome:
Specification Languages and Formal Verification
Logic Minimization
Testing and Verification
Electrical Simulation
Layout Synthesis
Behavioral Synthesis
Power-aware CAD
Analytical placement algorithms
Multi-level partitioning
Multi-level partitioning-based placement algorithms
Floorplanning algorithms/floorplan representations
Statistical timing analysis
Timing analysis crosstalk considerations
Retiming/pipelining algorithms
Floorplacement (integrated placement/floorplanning)
Wirelength estimation
Delay estimation
CAD techniques for yield enhancement
CAD techniques for dealing with process variations; statistical optimization
Congestion-aware placement
Incremental synthesis (eg, incremental placement, routing, etc)
Enhancements to FM partitioning
Technology mapping algorithms for standard cells
Boolean flexibilities through Boolean relations or SPFDs
Physical synthesis techniques
Layout-driven logic replication
Layout-driven retiming
Transistor-level optimizations:
Automatic sizing
Automatic threshold voltage selection
FPGA-related CAD
FPGA routing algorithms
Technology mapping
FPGA placement
Delay estimation
Clustering
Physical synthesis