34e57b94-711b-4eb7-99f2-c711f928208420210407073954543naunmdt@crossref.orgMDT DepositInternational Journal of Circuits, Systems and Signal Processing1998-446410.46300/9106http://www.naun.org/cms.action?id=3029118202111820211510.46300/9106.2021.15https://naun.org/cms.action?id=23283Power Consumption Improvements in AES Decryption Based on Null Convention LogicToi LeThanhFaculty of Electrical and Electronics Engineering, Ho Chi Minh City University of Technology (HCMUT), Vietnam National University Ho Chi Minh City, VietnamLac TruongTriFaculty of Electrical and Electronics Engineering, Ho Chi Minh City University of Technology (HCMUT), Vietnam National University Ho Chi Minh City, VietnamHoangTrangFaculty of Electrical and Electronics Engineering, Ho Chi Minh City University of Technology (HCMUT), Vietnam National University Ho Chi Minh City, VietnamIn this paper, we propose a new asynchronous method based on a Null Convention Logic (NCL) to improve power consumption for low power integrated circuits. The reason is because the NCL based designs do not use a clock, it eliminates the problems related to the clock and its power consumption reduces significantly. To show the advantages of the selected method, we propose two design models using the synchronous circuit design method, and the NCL based asynchronous circuit design method. To test these two design models conveniently, we also propose an extra automatic test model. In this study, the AES decryption is used as an example to illustrate both methods. The two above proposed AES decryption models are simulated and synthesized at the various corners by VCS and Design Compiler tool using TSMC standard cell libraries in 65nm technology. The synthesis results of the two above mentioned models indicated that the power consumption of the NCL based asynchronous circuit model is 3 times lower than that of the synchronous circuit model, and significantly improves (from 94% to 98%) compared with the results of the other authors. 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